 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| IDT54/74FCT821AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND INDUSTRIAL TEMPERATURE RANGES HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER FEATURES: * * * * IDT54/74FCT821AT/BT/CT DESCRIPTION: * * * * * A, B, and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: - Industrial: SOIC, SSOP, QSOP - Military: CERDIP, LCC The FCT821T series is built using an advanced dual metal CMOS technology. The FCT821T series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT821T is a buffered, 10-bit wide version of the popular FCT374T function. The FCT821T high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for lowcapacitance bus loading in high-impedance state. FUNCTIONAL BLOCK DIAGRAM OE CP 1 13 CP D0 2 23 D0 Y0 TO NINE O THER CHAN NELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND INDUSTRIAL TEMPERATURE RANGES 1 JUNE 2002 DSC-5486/2 (c) 2002 Integrated Device Technology, Inc. IDT54/74FCT821AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATION OE NC D1 D0 Y0 27 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 2 3 4 5 6 7 8 9 10 11 12 23 22 21 20 19 18 17 16 15 14 13 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 CP D2 D3 D4 NC D5 D6 D7 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 26 25 24 23 22 21 20 19 Y1 OE 1 24 VCC INDEX Vcc Y2 Y3 Y4 NC Y5 Y6 Y7 NC D8 D9 Y9 GND CERDIP/ SOIC/ SSOP/ QSOP TOP VIEW LCC TOP VIEW ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT Storage Temperature DC Output Current PIN DESCRIPTION Pin Name Dx CLR I/O I I Description D Flip-Flop Data Inputs When the clear input is LOW and OE is LOW, the Qx outputs are LOW. When the clear input is HIGH, data can be entered into the register. Clock Pulse for the Register. Enters data into the register on the LOW-to-HIGH transition Register 3-State Outputs Clock Enable. When the clock enable is LOW, data on the Dx input is transferred to the Qx input on the LOW-to-HIGH transition. When the clock enable is HIGH, the Qx inputs do not change state, regardless of the data or clock input transitions. Output Control. When the OE input is HIGH, the Yx outputs are in the high impedance state. When the OE input is LOW, the TRUE register data is present at the Yx outputs. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. CP Yx EN I O I OE I CAPACITANCE (TA = +25C, F = 1.0MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF NOTE: 1. This parameter is measured at characterization but not tested. 2 CP Y8 IDT54/74FCT821AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND INDUSTRIAL TEMPERATURE RANGES FUNCTION TABLE(1) OE H H H L H L H H L L CLR H H L L H H H H H H Inputs EN L L X X H H L L L L Dx L H X X X X L H L H CP X X X X Outputs Qx Yx L Z H Z L Z L L NC Z NC NC L Z H Z L L H H Function High Z Clear Hold Load NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance NC = No Change = LOW-to-HIGH transition DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10% Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State output pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) VCC = Min, IIN = -18mA -- VCC = Max., VIN = GND or VCC Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V Min. 2 -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01 Max. -- 0.8 1 1 1 1 1 -1.2 -- 1 A V mV mA Unit V V A A A OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC = Min VIN = VIH or VIL Test Conditions(1) IOH = -6mA MIL IOH = -8mA IND IOH = -12mA MIL IOH = -15mA IND IOL = 32mA MIL IOL = 48mA IND Min. 2.4 2 -- -60 -- Typ.(2) 3.3 3 0.3 -120 -- Max. -- -- 0.5 -225 1 V mA A Unit V VOL IOS IOFF Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5) VCC = Min VIN = VIH or VIL VCC = Max., VO = GND(3) VCC = 0V, VIN or VO 4.5V NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested. 3 IDT54/74FCT821AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND INDUSTRIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = EN = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE = EN = GND One Bit Toggling at fi = 5MHz VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle OE = EN = GND Eight Bits Toggling at fi = 2.5MHz VIN = 3.4V VIN = GND -- 6 16.3(5) VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 0.15 Max. 2 0.25 Unit mA mA/ MHz IC Total Power Supply Current(6) VIN = VCC VIN = GND -- 1.5 3.5 mA VIN = 3.4V VIN = GND VIN = VCC VIN = GND -- 2 5.5 -- 3.8 7.3(5) NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. 4 IDT54/74FCT821AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL Parameter Propagation Delay CP to Yx (OE = LOW) Condition(1) CL = 50pF RL = 500 CL = 300pF(3) RL = 500 CL = 50pF RL = 500 54/74FCT821AT Ind. Mil. (2) (2) Min. Max. Min. Max. 1.5 10 1.5 11.5 1.5 4 2 2 1.5 6 7 6 1.5 1.5 1.5 1.5 20 -- -- -- 14 -- -- -- 12 23 7 8 1.5 4 2 2 1.5 7 7 7 1.5 1.5 1.5 1.5 20 -- -- -- 15 -- -- -- 13 25 8 9 54FCT821BT Mil. (2) Min. Max. 1.5 8.5 1.5 3 1.5 0 1.5 6 6 6 1.5 1.5 1.5 1.5 16 -- -- -- 9.5 -- -- -- 9 16 7 8 54/74FCT821CT Ind. Mil. (2) (2) Min. Max. Min. Max. Unit 1.5 6 1.5 7 ns 1.5 3 1.5 0 1.5 6 6 6 1.5 1.5 1.5 1.5 12.5 -- -- -- 8 -- -- -- 7 12.5 6 6.5 1.5 3 1.5 0 1.5 6 6 6 1.5 1.5 1.5 1.5 13.5 -- -- -- 8.5 -- -- -- 8 13.5 6 6.5 ns ns ns ns ns ns ns ns ns tSU tH tH tPHL tREM tW tW tPZH tPZL Set-up Time HIGH or LOW Dx or EN to CP Hold Time HIGH or LOW, Dx to CP Hold Time HIGH or LOW, EN to CP Propagation Delay, CLR to Yx Recovery Time, CLR to CP Clock Pulse Width, HIGH or LOW CLR Pulse Width LOW Output Enable Time, OE to Yx tPHZ tPLZ Output Disable Time, OE to Yx CL = 50pF RL = 500 CL = 300pF(3) RL = 500 CL = 5pF(3) RL = 500 CL = 50pF RL = 500 NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This condition is guaranteed but not tested. 5 IDT54/74FCT821AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS V CC 500 VIN Pulse Generator RT D.U.T . VOUT 7.0V SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open 50pF CL 500 DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Octal link Test Circuits for All Outputs DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU tH tREM 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V Octal link LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE Octal link 1.5V 1.5V tSU tH Pulse Width Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V Octal link DISABLE 3V 1.5V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V tPLZ 0V 3.5V 0.3V VOL VOH 0V Octal link Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 6 IDT54/74FCT821AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER MILITARY AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION XXXX IDT XX FCT Device Type Temp. Range XX Package X Process Blank B Industrial MIL-STD-883, Class B Industrial Options Small Outline IC Quarter-size Small Outline Package Shrink Small Outline Package Military Options CERDIP Leadless Chip Carrier SO Q PY D L 821AT 821BT 821CT 54 74 High Performance CMOS Bus Interface Register - 55C to +125C - 40C to +85C DATA SHEET DOCUMENT HISTORY 6/25/2002 Updated as per PDNs Logic-00-07 and Logic-01-04 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: logichelp@idt.com (408) 654-6459 |
Price & Availability of 74FCT821TDS21895
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |